Published in Genetic and Evolutionary Computation Conference, 2020
The usage of Artificial Neural Networks (ANNs) with a fixed topology is becoming more popular in daily life. However, there are problems where it is difficult to build an ANN manually. Therefore, genetic algorithms like NeuroEvolution of Augmented Topologies (NEAT) have been developed to find topologies and weights. The downside of NEAT is that it often generates inefficient large ANNs for different problems. Read more
Published in Genetic and Evolutionary Computation Conference, 2021
Topology and Weight Evolving Artificial Neural Network (TWEANN) is a concept to find the topology and weights of Artificial Neural Networks (ANNs) using genetic algorithms. However, a well-known downside is that TWEANN algorithms often evolve inefficient large ANNs for large-scale problems and require long runtimes. Read more
Published in Asia and South Pacific Design Automation Conference, 2023
In recent years, hardware systems have significantly grown in complexity. Due to the increasing complexity, there is a need to continuously improve the quality of the hardware design process. This leads designers to strive for more efficient data structures and algorithms operating on them to guarantee the correct behavior of such systems through verification techniques like model checking and meet time-to-market constraints. A Binary Decision Diagram (BDD) is a suitable data structure as it provides a canonical compact representation of Boolean functions, given variable ordering, and efficient algorithms for manipulating them. However, reduced ordered BDDs also have challenges: There is a large memory consumption for the BDD construction of some complex practical functions and the use of realizations in the form of BDD packages strongly depends on the application. Read more
Published in International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
The complexity of hardware systems has increased significantly in recent decades. Due to increasing user requirements, there is a need to develop more efficient data structures and algorithms to guarantee the correct behavior of such systems. A Reduced Ordered Binary Decision Diagram (BDD) is a suitable data structure as it represents all Boolean functions canonically given a variable order as well as provides algorithms for efficient manipulation. However, BDDs also have challenges: practicability depends on their minimization and there is a large memory consumption for some complex functions. Read more
Published in Genetic and Evolutionary Computation Conference, 2023
In recent years, machine learning has become increasingly important in daily life. One of the most popular machine learning models used in many applications is an Artificial Neural Network (ANN). While in applications such as automatic speech recognition there is sufficient knowledge about the expected behavior for each input to use supervised learning, other applications like robot control define only an overall target so that the expected output for a given input can be ambiguous, making supervised learning inapplicable. Therefore, Topology and Weight Evolving ANN (TWEANN) has been developed in the past to evolve ANN topologies and connection weights. However, challenges of TWEANN are the design of genetic recombination and the exploration of huge search spaces for suitable solutions induced in particular by large-scale problems which can lead to impractical runtimes. Read more
It is necessary to develop more efficient data structures and associated verification algorithms to ensure correct behavior of increasingly complex hardware systems. A suitable data structure is a Binary Decision Diagram (BDD) because it can represent Boolean functions compactly and enables efficient algorithms to manipulate them. However, BDDs have challenges to overcome: practicability depends on their minimization and the reduction of large memory requirements for some complex functions. Read more
Published in International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2024
Tailoring hardware to an application significantly enhances its performance compared to using a general-purpose processor. While hardware optimization is essential to meet the user requirements for resource-constrained embedded systems, it generally entails considerable costs and a high level of effort. In recent work virtual prototypes have been shown to be an effective analysis tool for guiding this process. In best-case scenarios, it is possible to identify a single recurring instruction sequence that covers approximately 55 % of all executed instructions and is thus suitable for optimization by a Hardware Accelerator (HA). However, challenges arise for applications where each identified sequence only covers a small fraction of the total execution. In order to achieve comparable coverage, several HAs can be designed, but this also multiplies the hardware costs. To address these issues, this work proposes an approach to extend and merge identified sequences allowing the design of a single HA for the merged sequence. Experiments show that this approach significantly increases the coverage achievable with a single HA while the resulting performance loss is negligible compared to building multiple HAs. Read more
Tailoring hardware to applications significantly increases their performance, which is required to meet the rising demand for resource-limited devices in the area of embedded systems. While RISC-V facilitates application-specific solutions due to its extensibility, Virtual Prototypes (VPs) enable early software development before the actual hardware is built shortening the time-to-market. Although the RISC-V VP ecosystem already offers many useful tools to aid development there is still room for improvement, especially in analyzing applications for hardware optimization. To address the aforementioned issue and expand the mentioned ecosystem with a tool, this work presents RISC-V Opt-VP, which generates bounded execution trees in order to analyze applications. An embedded application analysis case study illustrates that promising instruction sequences are found which can also be merged to further improve their execution coverage, enabling efficient hardware designs. Read more
At Webmontag, enabled by bremen digitalmedia, I was invited to talk about securing web-based forms. In this context, I referred in particular to registration and login processes in web applications, i.e. to protect against unauthorized access. Read more
At hmmh multimediahaus, I talked about the functionality and countermeasures in terms of SQL injections. For this purpose, I demonstrated exemplary scenarios and showed how such attacks could have been prevented. Read more
At hmmh multimediahaus, I talked about risks and negative effects in terms of reverse engineering. Besides explaining basic concepts and presenting useful tools, I showed concretely how to recover source code and discussed protection mechanisms. Read more
In this lecture in the undergraduate course Computer Engineering 1 at University of Bremen, I repeated and deepened the contents concerning computer architecture and digital circuits for the exam preparation. Besides many other topics, computer system levels, pipelining, memory hierarchy, parallelism, encoding of characters/numbers, and the Boolean calculus were included. Read more
I presented our BugRunner Turbo 2 project at Projekttag Master Informatik. The project dealt with the development of own analysis tools and artificial intelligences to find bugs in games so that e.g. speedruns can be exploited to play games more efficiently. Read more
Together with Marcel Merten, I presented our work Scalable Neuroevolution of Ensemble Learners as a Group of Computer Architecture Talk at University of Bremen. In the context of evolutionary optimization, it addresses one of its main issues: lack of scalability. To this end – based on ALF – a framework was developed to heavily orchestrate genetic recombination for neural network combinations to effectively find suitable solutions. Moreover, ensemble learning methods restrict the search space. In a divide-and-conquer manner, the framework allows handling of large-scale machine learning problems. Read more
Undergraduate Course, University of Bremen, Department of Computer Science and Mathematics, 2017
This course is about computer architecture and digital circuits. The main aspects include, on the one hand, the different computer system levels / programming languages as well as how CPUs, caches, RAMs, hard drives etc. work together and, on the other hand, theoretical basics about Boolean algebra, logic synthesis, graph theory as well as how the previously introduced computer components can be constructed on this basis. Read more
